Some central processing units (CPUs) with high operating speeds require memory devices with extremely rapid access and retrieval characteristics. Memories which fulfill these requirements include small storage capacity, exceedingly fast access and retrieval random access memories (RAMs), commonly known as cache memories. The caches are used to store data and instructions which the CPU requires immediately. A larger, main memory stores the remaining portion of the currently running programs and supplies both the CPU and the cache memories with data and instructions which cannot be stored within the small cache memories. This system of memory hierarchy, with the fastest memories most closely linked to the CPU, has enabled computer systems to achieve very high operational speeds.
One known implementation of cache memories uses two separate caches, a data cache and an instruction cache, for supporting CPU operations - one cache supporting data operations and the other supporting instruction operations. This arrangement increases the computer's operating speed, but raises the possibility that data will be changed or updated in the data cache while it is also contained in the instruction cache. This can result in improper instructions being executed. The term "improper" is used to denote instructions that have not been updated.
It is an object of this invention to insure synchronism between the contents of separate data and instruction caches with a minimum amount of clearing of either cache.